The present invention relates to a thin film transistor (TFT) used for display devices such as a liquid crystal display (LCD) or an organic light emitting diode (OLED). More particularly, it relates to a thin film transistor including a polycrystalline silicon (i.e., polysilicon) active layer providing the source, drain and channel regions of the TFT, and to a method for making a TFT including the polycrystalline silicon active layer.
Thin film transistor (TFTs) used for display devices such as liquid crystal display (LCD) and organic light emitting diode (OLED) is formed by depositing a silicon layer on a transparent substrate such as a glass or quartz, forming a gate and a gate electrode on the silicon layer, implanting dopant in the source and the drain regions of the silicon layer, annealing the silicon layer to activate the dopant, and finally forming an insulation layer thereon. An active layer constituting the source, drain, and channel regions of a TFT is formed by depositing a silicon layer on a transparent substrate such as glass by chemical vapor deposition (CVD) technique. The silicon layer directly deposited on the substrate by the CVD technique is an amorphous silicon layer, which has low electron mobility. As a display device using thin film transistors requires a rapid operation speed and a miniaturized structure, the integration degree of its driving IC becomes higher and the aperture ratio of the pixel region becomes lower. Therefore, it is required to enhance the electron mobility of the silicon layer so that the driving circuit can be formed together with the pixel TFT of the display devices and that the pixel aperture ratio is increased. For this purpose, technologies for forming a polycrystalline silicon layer having high electron mobility by crystallizing an amorphous silicon layer with thermal treatment have been in use as described below.
Solid phase crystallization (SPC) method is used to anneal an amorphous silicon layer at a temperature of 600xc2x0 C. or below for a few hours or tens of hours. 600xc2x0 C. is the temperature causing deformation of the glass constituting the substrate. However, the SPC method has the following disadvantages. Since the SPC method requires a thermal treatment for a long time, the SPC method has low productivity. In addition, when annealing a large-sized substrate, the SPC method may cause deformation of the substrate during the extended thermal treatment even at a temperature of 600xc2x0 C. or below.
Excimer laser crystallization (ELC) method locally generates a high temperature on the silicon layer for a very short time by scanning an excimer laser beam to instantaneously crystallize the silicon layer. However, the ELC method has the following disadvantages. The ELC method has difficulties in accurately controlling the scanning of the laser beam. In addition, since the ELC method processes only one substrate at a time, the ELC method has relatively low productivity as compared to a method wherein a plurality of substrates are processed in a furnace at one time.
To overcome the aforementioned disadvantages of the conventional silicon crystallization methods, a method of inducing crystallization of an amorphous silicon layer at a low temperature about 200xc2x0 C. by contacting or implanting metals such as nickel, gold, and aluminum has been proposed. This phenomenon that low-temperature crystallization of amorphous silicon is induced with metal is conventionally called as metal induced crystallization (MIC). However, this metal induced crystallization (MIC) method also has following disadvantages. If a TFT is manufactured by the MIC method, the metal component used to induce the crystallization of silicon remains in the crystallized silicon providing the active layer of the TFT. The metal component remaining in the active layer causes current leakage in the channel region of the TFT.
Recently, a method of crystallizing a silicon layer by inducing crystallization of amorphous silicon in the lateral direction using a metal, which is conventionally referred to as xe2x80x9cmetal induced lateral crystallizationxe2x80x9d (MILC), was proposed. (See S. W. Lee and S. K. Joe, IEEE Electron Device Letter, 17(4), p. 160, 1996). In the metal induced lateral crystallization (MILC) phenomenon, metal does not directly cause the crystallization of the silicon, but the silicide generated by a chemical reaction between metal and silicon induces the crystallization of the silicon. As the crystallization proceeds, the silicide propagates in the lateral direction of the silicon inducing the sequential crystallization of the adjacent silicon region. As the metal causing this MILC, nickel and palladium or the like are known to those skilled in the art. Crystallizing a silicon layer by the MILC, a silicide containing crystallization inducing metal moves along the lateral direction as the crystallization of the silicon layer proceeds. Accordingly, little metal component is left in the silicon layer crystallized by the MILC. Therefore, the crystallized silicon layer does not adversely affect the current leakage or other characteristics of the TFT including the silicon layer. In addition, using the MILC, crystallization of silicon may be induced at a relatively low temperature of 300xc2x0 C.xcx9c500xc2x0 C. Thus, a plurality of substrates can be crystallized in a furnace at one time without causing any damages to the substrates.
FIG. 1A to FIG. 1D are cross-sectional views illustrating a conventional method for crystallizing a silicon active layer of TFT using the MIC and the MILC methods. Referring to FIG. 1A, an amorphous silicon layer 11 is formed on an insulation substrate 10 having a buffer layer (not shown) thereon. The amorphous silicon layer 11 is patterned by photolithography so as to form an active layer. A gate insulation layer 12 and a gate electrode 13 are formed on the active layer 11 by using conventional methods. As shown in FIG. 1B, the substrate is doped with impurity using the gate electrode 13 as a mask. Thus, a source region 11S, a channel region 11C and a drain region 11D are formed in the active layer. As shown in FIG. 1C, photoresist 14 is formed to cover the gate electrode 13, the source region 11S and the drain region 11D in the vicinity of the gate electrode 13, and a metal layer 15 is deposited over the substrate 10 and the photoresist 14. As shown in FIG. 1D, after removing the photoresist 14, the entire substrate is annealed at a temperature of 300-500xc2x0 C. As a result, the source and drain regions 16 covered with the residual metal layer 14 are crystallized by the MIC caused by the metal layer 14, and the metal-offset source and drain regions 15 not covered with the metal layer and a channel region 17 under the gate electrode 13 are respectively crystallized by the MILC propagating from the source and drain regions 16 covered with the metal layer 14.
The photoresist 14 is formed to cover source and drain regions adjacent to the gate electrode 13 in order to prevent the current leakage in the channel region and the degradation of the operation characteristics of the same. If the metal layer 15 is formed to cover the entire source and drain regions, the current leakage and the degradation of the operation characteristics occur because the metal component used to cause the MIC remains in the channel region 11C and the boundaries between the channel region and the source and the drain regions. Since the operation of the source and drain regions excluding the channel region are not substantially affected by the residual metal component, the source and drain regions apart from the channel region by a distance over 0.01xcx9c5 xcexcm is crystallized by the MIC caused by the MIC metal. Meanwhile, the channel region and the source and the drain regions adjacent to the channel region are crystallized by MILC induced by and propagating from the MIC metal. Crystallizing only the channel region and its vicinity by MILC, the time required to crystallize the entire active layer may be significantly reduced. However, when using the process shown in FIGS. 1A to 1D, a step of forming a photoresist layer, a step of patterning and removing the photoresist should be included in the conventional TFT fabrication process.
FIG. 2A is a TEM photograph of a nickel-silicide line formed in the channel region when crystallizing the silicon layer by the MILC as illustrated in FIGS. 1Axcx9c1D using Ni as the crystallization source metal. FIG. 2B illustrates the layout of a TFT, the active layer of which is crystallized by the method of FIGS. 1Axcx9c1D. The arrow in FIG. 2B indicates the crystallization direction by the MILC. As show in FIGS. 2Axcx9c2B, the nickel-silicide which induces the MILC of the active layer from the portions of the source and drain regions covered with the MIC metal moves toward the channel region as the MILC is progressed on both sides of the channel region. As a result, the nickel-silicide propagating from both sides of the channel region meets around the center of the channel region and forms a boundary in the channel region. A metal component contained in the nickel-silicide deteriorates the electrical characteristics of the channel region such as the field effect mobility and the threshold voltage, and thus adversely affect the performance of the TFT comprising such active layer.
To overcome the aforementioned disadvantages, a technique shown in FIGS. 3A to 3B has been proposed. Referring to FIG. 3A, an active layer 31, a gate insulation layer 32, and a gate electrode 33 are sequentially formed on a substrate 30. A photoresist pattern 34 is formed on the gate electrode 33 and the active layer 31, and a metal layer 35 is deposited to cover the substrate 30 and the photoresist pattern 34. As shown in FIG. 3A, the photoresist pattern 34 is formed to cover the gate electrode 33 and portions of the source and drain regions adjacent to the gate electrode 33. The photoresist is located at a position biased toward either the source region or the drain region. As shown in FIG. 3B, when the photoresist pattern 34 is removed by lift-off or other methods, metal offset areas 37 are formed in the portions of the source and drain regions adjacent to the channel region, and the metal layer 35 resides on the other areas of the source and drain regions. Annealing the substrate 30 in this state, the source and drain regions on which the metal layer 35 is formed are crystallized by the MIC cause by the MIC metal, and the metal-offset areas in the source and drain regions and the channel regions are respectively crystallized by the MILC phenomenon propagated from the MIC regions. As shown in FIG. 3C, since the metal offset area in either the source region or the drain region is broader than the other, the MILC boundary 36 between the crystallized regions may be located outside of the channel region 31C. By doing so, the degradation of the electrical characteristic of the channel area 31C caused by the MILC boundary may be prevented. However, in order to use the process shown in FIGS. 3A to 3C, steps of forming, patterning and removing a photoresist layer also should be included in the conventional TFT fabrication process.
It is an object of the present invention to provide a thin film transistor including a crystallized active layer and a method for making the same, which overcomes aforementioned problems. The method of the present invention can simultaneously perform the crystallization of a plurality of substrates using MIC and MILC at a lower temperature than those used by the SPC and the ELC methods. Thus, it becomes possible to manufacture poly-silicon TFT""s at a low cost without damaging the substrate.
It is another object of the present invention to provide a poly-silicon TFT and a method for making the same, which does not have the MIC metal component and the MILC boundary in the a channel region, without requiring the processes of forming, patterning and removing a photoresist mask.
In order to achieve these objects, the present invention provides a method for fabricating a TFT comprising the steps of a) providing a substrate; (b) depositing an amorphous silicon layer on the substrate to provide an active layer of the TFT including a source, drain and channel regions; (c) forming a gate insulation layer and a gate electrode on the substrate and the active layer; (d) doping impurity in the source and drain regions of the active layer; (e) forming a contact insulation layer on the substrate, the active layer and the gate electrode and forming contact holes in the contact insulation layer to expose portions of the source and drain regions; (f) applying MILC source metal on the portions of the source and drain regions exposed by the contact holes; (g) conducting thermal treatment of the substrate and the active layer to crystallize the active layer formed of amorphous silicon; and (h) forming contact electrodes electrically connected to the source and the drain regions through the contact holes.
In other aspect of the invention, the present invention provides a thin film transistor comprising a substrate; a polysilicon active layer formed on said transparent substrate and including a source, drain and channel regions of the TFT; a gate insulation layer and a gate electrode formed on the substrate and the active layer; a contact insulation layer covering the substrate, the active layer and the gate electrode and including contact holes formed to expose portions of the source and the drain regions; and contact electrodes electrically connected to the source and the drain regions through said contact holes, wherein the active layer of the TFT is formed by crystallizing an amorphous silicon layer formed on the substrate by conducting a thermal treatment of the amorphous silicon layer, and the thermal treatment causes a MILC propagating from the portions of the source and drain regions exposed by the contact holes and having MILC source metal formed thereon.
Additional features and advantages of the present invention will be set forth or will be apparent from below detailed description of the invention. The objectives and other advantages of the invention will be realized and attained by the scheme particularly pointed out in the written description and claims hereof as well as the appended drawings.